1. Field of the Invention
The present invention relates generally to methods for forming dielectric layers within microelectronic fabrications. More particularly, the present invention relates to methods for forming, with enhanced stability, halogen doped glass dielectric layers within microelectronic fabrications.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
As microelectronic fabrication integration levels have increased and microelectronic device and patterned microelectronic conductor layer dimensions have decreased, it has become increasingly important within the art of microelectronic fabrication to form interposed between the patterns of patterned microelectronic conductor layers within microelectronic fabrications microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials. Dielectric layers formed of comparatively low dielectric constant dielectric materials are desirable formed interposed between the patterns of patterned microelectronic conductor layers within microelectronic fabrications since such dielectric layers assist in providing microelectronic fabrications possessing enhanced microelectronic fabrication speed and attenuated patterned microelectronic conductor layer cross-talk.
Of the comparatively low dielectric constant dielectric materials potentially applicable for forming dielectric layers interposed between the patterns of patterned microelectronic conductor layers within microelectronic fabrications, halogen doped glass dielectric materials, and in particular fluorosilicate glass (FSG) dielectric materials, are presently of considerable interest. Halogen doped glass dielectric materials are presently of considerably interest for forming dielectric layers of comparatively low dielectric constant formed interposed between the patterns of patterned microelectronic conductor layers within microelectronic fabrications since in addition to possessing a comparatively low dielectric constant, halogen doped glass dielectric materials, and in particular fluorosilicate glass (FSG) dielectric materials, may typically be readily formed employing deposition methods, such as but not limited to chemical vapor deposition (CVD) methods, as are otherwise conventional in the art of microelectronic fabrication.
For comparison purposes, while fluorosilicate glass (FSG) dielectric materials may be employed for forming dielectric layers within microelectronic fabrications, where the dielectric layers have a bulk dielectric constant of from about 3.5 to about 3.8, conventional silicon containing dielectric materials as employed within microelectronic fabrication, such as but not limited to silicon oxide dielectric materials, silicon nitride dielectric materials and silicon oxynitride dielectric materials as employed within microelectronic fabrications, typically provide within microelectronic fabrications dielectric layers having a bulk dielectric constant of from about 4.0 to about 6.0.
While fluorosilicate glass (FSG) dielectric materials are thus particularly desirable in the art of microelectronic fabrication for forming low dielectric constant dielectric layers interposed between the patterns of patterned microelectronic conductor layers within microelectronic fabrications, fluorosilicate glass (FSG) dielectric materials in particular, and halogen doped glass dielectric materials more generally, are nonetheless not entirely without problems in the art of microelectronic fabrication for forming low dielectric constant dielectric layers formed interposed between the patterns of patterned microelectronic conductor layers within microelectronic fabrications. In that regard, it known in the art of microelectronic fabrication that halogen doped glass dielectric materials, such as fluorosilicate glass (FSG) dielectric materials, when employed for forming dielectric layers within microelectronic fabrications suffer from instability which leads to problems such as but not limited to: (1) outgassing of mobile halogen (i.e. fluorine) species from halogen doped glass dielectric materials such as a fluorosilicate glass (FSG) dielectric materials, which outgassing might lead to increases in dielectric constant of the halogen doped glass dielectric materials; and (2) moisture sorbtion into ambiently exposed halogen doped glass dielectric materials which might lead to formation of acidic (i.e. hydrofluoric acid) reaction products within the halogen doped glass dielectric materials.
It is thus towards the goal of forming within microelectronic fabrications low dielectric constant dielectric layers formed employing halogen doped glass dielectric materials, and more particularly fluorosilicate glass (FSG) dielectric materials, while forming the low dielectric constant dielectric layers with enhanced stability, that the present invention is directed.
Various methods have been disclosed in the art of microelectronic fabrication for forming dielectric layers with desirable properties within microelectronic fabrications.
For example, Ravi et al., in U.S. Pat. No. 5,661,093, discloses a method for forming within a microelectronic fabrication a halogen doped glass dielectric layer, such as a fluorosilicate glass (FSG) dielectric layer, with enhanced resistance to moisture absorption into the halogen doped glass dielectric layer and enhanced resistance to halogen dopant outgassing from the halogen doped glass dielectric layer. The method employs when forming the halogen doped glass dielectric layer a multiplicity of sub-layers of the halogen doped glass dielectric layer, wherein each sub-layer of the halogen doped glass dielectric is separated from an adjoining sub-layer within of the halogen doped glass dielectric layer by a sealing layer within the halogen doped glass dielectric layer.
In addition, Lou, in U.S. Pat. No. 5,759,906, discloses a method for forming within a microelectronic fabrication a sandwich composite planarizing dielectric layer construction which incorporates a spin-on-glass (SOG) planarizing dielectric layer within the sandwich composite planarizing dielectric layer construction, where when forming a via through the sandwich composite planarizing dielectric layer construction there is attenuated within the via outgassing from the spin-on-glass (SOG) planarizing dielectric layer. The method realizes the foregoing result by: (1) employing when forming the spin-on-glass (SOG) planarizing dielectric layer within the sandwich composite planarizing dielectric layer construction a multi-layer spin-on-glass (SOG) planarizing dielectric layer, where each sub-layer within the multi-layer spin-on-glass (SOG) planarizing dielectric layer is cured at an elevated temperature for an elongated time period; and (2) employing after forming the via through the sandwich composite planarizing dielectric layer construction a dielectric sidewall spacer layer formed into the via to passivate portions of the spin-on-glass planarizing dielectric layer exposed within the via.
Further, Guo et al., in U.S. Pat. No. 5,763,010, discloses yet another method for forming, with enhanced stability with respect to halogen dopant outgassing, a halogen doped glass dielectric layer, such as a fluorosilicate glass (FSG) dielectric layer, within a microelectronic fabrication. The method employs a thermal annealing of the halogen doped glass dielectric layer at a temperature of about 300 to about 550 degrees centigrade, presumably to remove loosely bound halogen atoms which would otherwise outgas from within the halogen doped glass dielectric layer.
Yet further, Chen et al., in U.S. Pat. No. 5,858,869, discloses a method for forming, with enhanced process latitude and with enhanced dielectric properties, a sandwich composite planarizing dielectric layer construction formed upon a topographic substrate layer within a microelectronic fabrication. The method employs when forming the sandwich composite planarizing dielectric layer construction an anisotropically deposited silicon oxide layer formed upon the topographic substrate layer and employed as a liner layer within the sandwich composite planarizing dielectric layer construction, where the anisotropically deposited silicon oxide layer has a greater thickness upon upper lying horizontal features within the topographic substrate layer than upon vertical sidewall features within the topographic substrate layer.
Finally, Chou et al., in U.S. Pat. No. 5,861,345, discloses a method for forming within a microelectronic fabrication a sandwich composite planarizing dielectric layer construction with: (1) a reduced susceptibility to delamination of dielectric layers within the sandwich composite planarizing dielectric layer construction; and (2) a reduced susceptibility of cracking within a spin-on-glass (SOG) planarizing dielectric layer employed within the sandwich composite planarizing dielectric layer construction. The method employs when forming the sandwich composite planarizing dielectric layer construction either of a nitrous oxide plasma treatment or hexafluoroethane plasma treatment of the spin-on-glass (SOG) planarizing dielectric layer within the sandwich composite planarizing dielectric layer construction prior to forming in-situ upon the plasma treated spin-on-glass (SOG) planarizing dielectric layer so formed a capping dielectric layer formed employing a plasma enhanced chemical vapor deposition (PECVD) method.
Desirable in the art of microelectronic fabrication are additional methods and materials which may be employed for forming within microelectronic fabrications halogen doped glass dielectric layers, such as but not limited to fluorosilicate glass (FSG) dielectric layers, with enhanced stability.
It is towards the foregoing object that the present invention is directed.